The structures and methods disclosed herein relate to lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETS) and, more particularly, to an LDMOSFET with a below-source isolation region (e.g., a below-source air-gap isolation region) for reduced parasitic capacitance and a method of forming the LDMOSFET.
Typically, a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET), like a conventional MOSFET, comprises a channel region positioned laterally between a source region and a drain region. However, unlike the conventional MOSFET, the LDMOSFET is asymmetrical. Specifically, the drain region (e.g., an N-type drain region) of the LDMOSFET is separated from the channel region by a relatively low-doped drain drift region (e.g., an N-type drain drift region with a lower conductivity level than the drain region), which provides ballasting resistance so that the LDMOSFET has a relatively high blocking voltage (i.e., a high maximum voltage that can be applied to the transistor). To form such an LDMOSFET structure on a bulk semiconductor substrate (e.g., on a P-type semiconductor substrate), the source region (e.g., an N+ source region) is typically formed above multiple well regions with different type conductivities (e.g., above a P-well region that is above an N-well region that is above a lower portion of the P-type semiconductor substrate). In combination, these well regions and the semiconductor substrate form a vertical capacitor (e.g., a PNP capacitor) that turns on during switching of the LDMOSFET, generating parasitic capacitance and, thereby causing power loss. Therefore, there is a need in the art for an LDMOSFET with reduced parasitic capacitance and a method of forming the LDMOSFET.